Hard skills

Programming Languages: C/C++, Python, Assembly (RISC-V, MIPS)

 
 
 

Hardware Description Languages: SystemVerilog, Verilog

 
 
 

soft skills

Teamwork

 
 
 

Problem-solving

 
 
 

Logical Thinking

 
 
 

Self-learning

 
 
 

Time Management

 
 
 

English

 
 
 

CERTIFICATEs

TOEIC Speaking and Writing: 320/400

 
 
 

references

TÊN

Chức vụ

  • An internship at Ampere will allow me to pursue my great passion for the challenges of verification process. I am flexible and open to learning from mentors and leaders in the field.
  • I hope to obtain an internship at Ampere to improve my practical work skills further and have a chance to become your employee in the future.
 
 
 
 

VNU-HCM University of Information Technology

(09.2021 – Now)

Major: Computer Engineering

GPA: 9.3/10

 
 
 
 
 
 
  • Basic knowledge of computer architecture, CPU components, their design and operation.
  • Understand clearly about Cache memory structures, Memory Management Unit (MMU).
  • Ability to use Hardware Description Languages (HDL) like Verilog or SystemVerilog to design and verify designs.
  • Understand about components in SystemVerilog Environment, their function and operation
  • Ability to understand and design sequential circuits, combinational circuits, and finite-state machines (FSM).
  • Ability to use some high-level programming languages such as C/C++ or Python.
  • Having experience with MIPS or RISC-V Instruction Set.
 
 
 
 
 
 
 
 
 
 
 
 

DESIGN AND IMPLEMENTATION OF CACHE COHERENCE PROTOCOL FOR MULTICORE PROCESSOR USING MOESISNOOPY PROTOCOL

  • Description: The design supports data synchronization between cores in a multicore system using the MOESI algorithm and multiway set associative cache architecture.
  • My role: I independently perform in the design process of multiway set associative cache architecture and cooperate with my partner to implement MOESI algorithm on this cache architechture to support data synchronization in a multicore system.
  • Tool used: Vivado
  • Result: The project is underway and is in the phase of using Verilog for RTL design and testing.
 
 
 
 
 
 

SINGLE CYCLE RISC-V AND PIPELINE MIPS PROCESSORS DESIGN AND SIMULATION

  • Description: Both designs have ability to support 32I Instruction Set with  basic instruction like add, sub, or, and, slt, addi, ori, andi, lw, sw, beq, bne, lui, jal.
  • My role: I designs both projects using Verilog for RTL design and testing.
  • Tool used: Vivado, Quartus and ModelSim
  • Result: Both projects were completed and met initial requirements.
 
 
 

MIPS AND RISC-V ASSEMBLLERS

  • Description: Both designs have ability to convert  full MIPS and RISC-V 32I Instruction Set to machine code. MIPS assembler is implemented with C/C++ language while RISC-V assembler is performed by Python language.
  • My role: I read the specification documents of MIPS and RISC-V 32I Instruction Set and use C/C++, Python to write both assemblers.
  • Tool used: DevC++ and Pycharm
  • Result: Both projects were completed and met initial requirements.